DS016 (v1.8) january 8, 2002 www.xilinx.com 1 preliminary product specification 1-800-255-7778 ? 2002 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? lowest power 128 macrocell cpld 6.0 ns pin-to-pin logic delays system frequencies up to 145 mhz 128 macrocells with 3,000 usable gates available in small footprint packages - 144-pin tqfp (108 user i/o pins) - 144-ball cs bga (108 user i/o) - 100-pin vqfp (84 user i/o) optimized for 3.3v systems - ultra low power operation - 5v tolerant i/o pins with 3.3v core supply - advanced 0.35 micron five layer metal eeprom process - fast zero power? (fzp) cmos design technology advanced system features - in-system programming - input registers - predictable timing model - up to 23 available clocks per function block - excellent pin retention during design changes - full ieee standard 1149.1 boundary-scan (jtag) - four global clocks - eight product term control terms per function block fast isp programming times port enable pin for additional i/o 2.7v to 3.6v supply voltage at industrial temperature range programmable slew rate control per output security bit prevents unauthorized access refer to xpla3 family data sheet ( ds012 ) for architecture description description the xcr3128xl is a 3.3v 128 macrocell cpld targeted at power sensitive designs that require leading edge program- mable logic solutions. a total of eight function blocks provide 3,000 usable gates. pin-to-pin propagation delays are 6.0 ns with a maximum system frequency of 145 mhz. totalcmos design technique for fast zero power xilinx offers a totalcmos cpld, both in process technol- ogy and design technique. xilinx employs a cascade of cmos gates to implement its sum of products instead of the traditional sense amp approach. this cmos gate imple- mentation allows xilinx to offer cplds that are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. refer to figure 1 and table 1 showing the i cc vs. frequency of our xcr3128xl totalcmos cpld (data taken with eight resetable up/down, 16-bit counters at 3.3v, 25 c). 0 xcr3128xl 128 macrocell cpld DS016 (v1.8) january 8, 2002 014 preliminary product specification r figure 1: typical i cc vs. frequency at v cc = 3.3v, 25 c frequency (mhz) DS016_01_112100 typical i cc (ma) 0 0 10 20 30 50 70 40 60 120 140 100 80 60 40 20 table 1: typical i cc vs. frequency at v cc = 3.3v, 25 c frequency (mhz) 0 1 5 10 20 40 60 80 100 120 140 ty p ic a l i cc (ma) 0 0.5 2.2 4.4 8.7 17.1 25.3 33.6 41.6 49.7 57.7
xcr3128xl 128 macrocell cpld 2 www.xilinx.com DS016 (v1.8) january 8, 2002 1-800-255-7778 preliminary product specification r dc electrical characteristics over recommended operating conditions (1) symbol parameter test conditions min. max. unit v oh ( 2 ) output high voltage i oh = ? 8 ma 2.4 - v v ol output low voltage for 3.3v outputs i ol = 8 ma - 0.4 v i il input leakage current v in = gnd or v cc ? 10 10 a i ih i/o high-z leakage current v in = gnd or v cc ? 10 10 a i ccsb standby current v cc = 3.6v - 100 a i cc dynamic current ( 3 , 4 ) f = 1 mhz - 1 ma f = 50 mhz - 30 ma c in input pin capacitance ( 5 ) f = 1 mhz - 8 pf c clk clock input capacitance ( 5 ) f = 1 mhz - 12 pf c i/o i/o pin capacitance ( 5 ) f = 1 mhz - 10 pf notes: 1. see xpla3 family data sheet ( ds012 ) for recommended operating conditions. 2. see figure 2 for output drive characteristics of the xpla3 family. 3. see table 1 , figure1 for typical values. 4. this parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and unloaded. inputs are tied to v cc or ground. this parameter guaranteed by design and characterization, not testing. 5. typical values, not tested. figure 2: typical i/v curve for the xpla3 family 0 0 1 0 2 0 30 4 0 50 60 7 0 80 90 1 00 0 . 5 1 1. 5 2 2. 5 3 3 . 5 4 4. 5 5 volt s i o l ( 3.3v ) i o h ( 3.3v ) i o h ( 2.7v ) ma ds012 _ 10 _ 04190 1
xcr3128xl 128 macrocell cpld DS016 (v1.8) january 8, 2002 www.xilinx.com 3 preliminary product specification 1-800-255-7778 r ac electrical characteristics over recommended operating conditions (1,2) symbol parameter -6 -7 -10 unit min. max. min. max. min. max. t pd1 propagation delay time (single p-term) - 5.5 - 7.0 - 9.1 ns t pd2 propagation delay time (or array) (3) -6.0-7.5-10.0ns t co clock to output (global synchronous pin clock) - 4.0 5.0 - 6.5 ns t suf setup time (fast input register) 2.5 - 3.0 - 3.0 - ns t su1 (4) setup time (single p-term) 3.5 - 4.3 - 5.4 - ns t su2 setup time (or array) 4.0 - 4.8 - 6.3 - ns t h (4) hold time 0-0-0-ns t wlh (4) global clock pulse width (high or low) 2.5 - 3.0 - 4.0 - ns tt plh (4) p-term clock pulse width 4.0 - 5.0 - 6.0 - ns t r (4) input rise time - 20 - 20 - 20 ns t l (4) input fall time - 20 - 20 - 20 ns f system (4) maximum system frequency - 145 - 119 - 95 mhz t config (4) configuration time (5) -60-60-60 s t init (4) isp initialization time - 60 - 60 - 60 s t poe (4) p-term oe to output enabled - 7.5 - 9.3 - 11.2 ns t pod (4) p-term oe to output disabled (6) -7.5-9.3-11.2ns t pco (4) p-term clock to output - 6.5 - 8.3 - 10.7 ns t pao (4) p-term set/reset to output valid - 8.0 - 9.3 - 11.2 ns advance preliminary notes: 1. specifications measured with one output switching. 2. see xpla3 family data sheet ( ds012 ) for recommended operating conditions. 3. see figure 4 for derating. 4. these parameters guaranteed by design and/or characterization, not testing. 5. typical current draw during configuration is 9 ma at 3.6v. 6. output c l = 5 pf.
xcr3128xl 128 macrocell cpld 4 www.xilinx.com DS016 (v1.8) january 8, 2002 1-800-255-7778 preliminary product specification r internal timing parameters (1,2) symbol parameter -6 -7 -10 unit min. (3) max. (3) min. max. min. max. buffer delays t in input buffer delay - 1.3 - 1.6 - 2.2 ns t fin fast input buffer delay - 2.3 - 3.0 - 3.1 ns t gck global clock buffer delay - 0.8 - 1.0 - 1.3 ns t out output buffer delay - 2.2 - 2.7 - 3.6 ns t en output buffer enable/disable delay - 4.2 - 5.0 - 5.7 ns internal register and combinatorial delays t ldi latch transparent delay - 1.3 - 1.6 - 2.0 ns t sui register setup time 1.0 - 1.0 - 1.2 - ns t hi register hold time 0.3 - 0.5 - 0.7 - ns t ecsu register clock enable setup time 2.0 - 2.5 - 3.0 - ns t echo register clock enable hold time 3.0 - 4.5 - 5.5 - ns t coi register clock to putput delay - 1.0 - 1.3 - 1.6 ns t aoi register async. s/r to output delay - 2.5 - 2.3 - 2.1 ns t rai register async. recovery - 4.0 - 5.0 - 6.0 ns t logi1 internal logic delay (single p-term) - 2.0 - 2.7 - 3.3 ns t logi2 internal logic delay (pla or term) - 2.5 - 3.2 - 4.2 ns feedback delays t f zia delay - 1.7 - 2.1 - 3.0 ns time adders t logi3 fold-back nand delay - 6.0 - 7.5 - 9.5 ns t uda universal delay - 1.7 - 2.2 - 2.7 ns t slew slew rate limited delay - 4.0 - 5.0 - 6.0 ns advance preliminary notes: 1. these parameters guaranteed by design and/or characterization, not testing. 2. see xpla family data sheet ( ds012 ) for timing model. 3. contact xilinx for update on advance specification.
xcr3128xl 128 macrocell cpld DS016 (v1.8) january 8, 2002 www.xilinx.com 5 preliminary product specification 1-800-255-7778 r switching characteristics figure 3: ac load circuit DS016_03_102401 component values r1 390 ? r2 390 ? c1 35 pf measurement s1 s2 t poe (high) t poe (low) t p open closed closed open closed closed v cc v out v in c1 r1 r2 s1 s2 note: for t pod , c1 = 5 pf. delay measured at output level of v ol + 300 mv, v oh ? 300 mv. figure 4: derating curve for t pd2 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.2 7.0 7.4 1248 DS016_04_042800 16 number of adjacent outputs switching ns figure 5: voltage waveform 90% 10% 1.5 ns 1.5 ns DS016_05_042800 +3.0v 0v measurements: all circuit delays are measured at the +1.5v level of inputs and outputs, unless otherwise specified. t r t l
xcr3128xl 128 macrocell cpld 6 www.xilinx.com DS016 (v1.8) january 8, 2002 1-800-255-7778 preliminary product specification r pin descriptions table 2: xcr3128xl user i/o pins vq100 cs144 tq144 total user i/o pins 84 108 108 table 3: xcr3128xl i/o pins function block macrocell vq100 cs144 tq144 1 1 - b12 106 1273 (1) d11 (1) 104 (1) 1372d12102 1471d13101 1570e10100 1669e1199 1768e1298 18--- 19--- 110 - - - 1 11 67 e13 97 112 -f1096 1 13 65 f12 94 1 14 64 f13 93 11563g1092 116 -g1191 2175a13107 2276a12109 2377b11110 2478a11111 2579d10112 2680c10113 2781b10114 28--- 29--- 210 - - - 21183d9116 21284c9117 21385b9118 214 -a9119 215 -d8120 216 -c8121 31 -g1390 3262 (1) g12 (1) 89 (1) 3361h1388 3460h1287 35 -h1186 3658j1384 3757j1283 38 --- 39 --- 310- - - 31156j1182 31255j1081 31354k1380 31453k1279 31552k1178 316-k1077 41 -m860 4 2 40 l8 61 4341k862 4442n963 4 5 44 l9 65 4645k966 4746n1067 48 --- 49 --- 410- - - 41147m1068 4 12 48 l10 69 41349n1170 41450m1171 415-l1172 416-m1274 512a11 521a2143 5 3 100 c3 142 5 4 99 b3 141 5 5 98 a3 140 ta ble 3 : xcr3128xl i/o pins (continued) function block macrocell vq100 cs144 tq144
xcr3128xl 128 macrocell cpld DS016 (v1.8) january 8, 2002 www.xilinx.com 7 preliminary product specification 1-800-255-7778 r 5 6 97 c4 139 5 7 96 b4 138 58--- 59--- 510 - - - 511 -a4137 512 -d5136 51394b5134 51493a5133 51592d6132 516 -c6131 61-b12 624 (1) d2 (1) 4 (1) 6 3 5d15 6 4 6e46 6 5 7e37 6 6 8e28 6 7 9e19 68--- 69--- 610 - - - 6 11 10f410 612 -f311 613 -f212 6 14 12g214 6 15 13g115 6 16 14g316 71-n756 7 2 37 m7 55 7 3 36 n6 54 7 4 35 m6 53 7 5 33 m5 46 7 6 32 l5 45 7 7 31 k5 44 78--- 79--- 710 - - - table 3: xcr3128xl i/o pins (continued) function block macrocell vq100 cs144 tq144 71130n442 7 12 29m441 7 13 28l440 7 14 27k439 715-n338 716-m337 81 -h118 8215 (1) h2 (1) 20 (1) 8316h321 8417h422 85 -j123 8619j325 8720j426 88 --- 89 --- 810- - - 8 11 21k127 8 12 22k228 8 13 23k329 8 14 24l130 8 15 25m231 816-n132 notes: 1. jtag pins ta ble 3 : xcr3128xl i/o pins (continued) function block macrocell vq100 cs144 tq144
xcr3128xl 128 macrocell cpld 8 www.xilinx.com DS016 (v1.8) january 8, 2002 1-800-255-7778 preliminary product specification r table 4: xcr3128xl global, jtag, port enable, power, and no connect pins pin type vq100 cs144 tq144 in0 / clk0 90 d7 128 in1 / clk1 89 c7 127 in2 / clk2 88 a7 126 in3 / clk3 87 b7 125 tck 62 g12 89 tdi 4 d2 4 tdo 73 d11 104 tms 15 h2 20 port_en 11 (1) f1 (1) 13 (1) vcc 3, 18, 34, 39, 51, 66, 82, 91 a10, b2, b6, b8, d4, f11, j2, k6, k7, l13, n5, n12 24, 50, 51, 58, 73, 76, 95, 115, 123, 130, 144 gnd 26, 38, 43, 59, 74, 86, 95 a6, a8, c5, c13, d3, g4, h10, l6, l7, m9, n2, n8 3, 17, 33, 52, 57, 59, 64, 85, 105, 124, 129, 135 no connects - b13, c1, c2, c11, c12, l2, l3, l12, m1, m13, n13 19, 34, 35, 36, 43, 47, 48, 49, 75, 103, 108, 122 notes: 1. port enable is brought high to enable jtag pins when jtag pins are used as i/o. see family data sheet ( ds012 ) for full explanation. ta ble 4 : xcr3128xl global, jtag, port enable, power, and no connect pins pin type vq100 cs144 tq144
xcr3128xl 128 macrocell cpld DS016 (v1.8) january 8, 2002 www.xilinx.com 9 preliminary product specification 1-800-255-7778 r ordering information component availability xcr3128xl -7 vq 100 c example: temperature range number of pins package type device type speed grade device ordering options speed package temperature -10 10 ns pin-to-pin delay vq100 100-pin very thin quad flat package c = commercial t a = 0 c to +70 c v cc = 3.0v to 3.6v -7 7.5 ns pin-to-pin delay cs144 144-ball chip scale package i = industrial t a = ? 40 c to +85 c v cc = 2.7v to 3.6v -6 6 ns pin-to-pin delay tq144 144-pin thin quad flat pack pins 100 144 144 type plastic vqfp plastic tqfp plastic bga code vq100 tq144 cs144 xcr3128xl -6 (c) (c) (c) -7 c, (i) c, (i) c, (i) -10 c,i c,i c,i notes: 1. parenthesis indicate future planned products. please contact xilinx for up-to-date information.
xcr3128xl 128 macrocell cpld 10 www.xilinx.com DS016 (v1.8) january 8, 2002 1-800-255-7778 preliminary product specification r revision history the following table shows the revision history for this document. date version revision 04/07/00 1.0 initial xilinx release. 05/03/00 1.1 minor updates and added boundary scan to pinout table. 11/20/00 1.2 updated pinout tables; corrected note in ta ble 4 to read: "port enable pin is brought high". 12/08/00 1.3 updated pinout tables. 01/17/01 1.4 removed timing model. 04/11/01 1.5 added typical i/v curve, figure 2 ; added table 2 : total user i/o; changed v oh spec. 04/19/01 1.6 updated typical i/v curve, figure 2 : added voltage levels. 08/10/01 1.7 moved figure 1 and ta ble 1 to first page. changed vq144 to vq100 in ta bl e 2 . 01/08/02 1.8 updated t suf and t fin spec to match software timing. added single p-term setup time (t su1 ) to ac table, renamed t su to t su2 for setup time through the or array. added t init spec. updated t config spec. updated t hi spec to correct a typo. updated ac load circuit diagram to more closely resemble true test conditions, added note for t pod delay measurement.
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